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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66006P/FP M66006P/FP
12-BIT I/O EXPANDER 12-BIT I/O EXPANDER
DESCRIPTION The M66006 is a semiconductor integrated circuit which has 12-bit shift register function to execute serial-parallel conversion and parallel-serial conversion. Because a serial-parallel shift register and a parallel-serial shift register are independently built in this IC, it is possible to read serial input data to a shift register while converting parallel data into serial data. Also, parallel data I/O pins can be set to input mode or output mode bit-by-bit. The M66006 can be widely used for I/O port expansion of MCU, serial bus system data communication, etc. FEATURES * Bi-directional serial data communication with MCU * Read of serial data during parallel-serial conversion. * Bit resolution of serial data I/O * Low power dissipation (50W/package max.) (VCC=5V, Ta=25C, in quiescing) * Schmitt input (DI, CLK, S, CS) * Open drain output (DO, from D1 to D12) * Parallel data I/O (from D1 to D12) * Wide operating supply voltage range (VCC=2 to 6V) * Wide operating temperature range (Ta =-20 to 75C) APPLICATION Serial-parallel data conversion, parallel-serial data conversion, serial bus control by MCU. BLOCK DIAGRAM
PIN CONFIGURATION (TOP VIEW)
DO 1 DI 2 CS 4 VCC
Set input 5 20 D1 19 D2 18 D3 17 D4 16 15 14 13 12 11
D5 Parallel data I/O D6 D7 D8 D9 D10
Serial data output Serial data input
DO DI CLK CS
D1 D2 D3 D4 D5
Clock input CLK 3 Chip select input
S 6 GND
7
S
D6 D7
Parallel data D12 outputs D11
8 9
10
D12 D11
D8 D9 D10
GND
Outline 20P4 20P2N-A
VCC 5
Control circuit
Clock input CLK 3 Set input S6
Shift register ! D12 D11 D10
DO
Serial 1 DOdata output 20 D1 19 18
D2 D3 D10 D11 D12
D3 D2 D1
VCC CLK S CS DI
Chip select input CS 4
Q12 Q11 Q10 D12 D11 D10 Q12 D11 D10 D1 DI 2
Q3 Q2 Q1 D3 D2 D1 Q3 Q2 Q1 11 9 8 7 GND 10 GND
Parallel output latch
Parallel data I/O
Input form
VCC DO
VCC D1~D12
Shift register @ Serial data input
Output form
1
MITSUBISHI DIGITAL ASSP
M66006P/FP
12-BIT I/O EXPANDER
FUNCTION The M66006 realizes low power dissipation and high noise immunity by applying silicon CMOS process. Because a 12-bit serial-parallel shift register and a 12-bit parallel-serial shift register are independently built in this IC, it is possible to read serial input data while converting parallel data into serial data. When CS changes from "H" to "L", serial output of 12-bit parallel data and read of serial data from the MCU start. That is, 12-bit parallel data is latched at the falling edge of CS, synchronized with the falling edge of shift clock, and then output to serial output pin DO as serial data. At the same time, serial data from the MCU is read to the internal shift register at the rising edge of shift clock. The shift clock on and after 13th bit is neglected and pin DO is put in the high impedance state when the reading operation is masked. When CS changes from "L" to "H", 12-bit serial data read into pin DI is output to parallel output pins from D1 to D12. Because the output form of parallel output pins is N-channel open drain output, "H" must be written to the pin to set to input mode.
DESCRIPTION OF OPERATION (1) When power is supplied, pins DO and from D1 to D12 are in undefined state. When S changes to "L", those pins are in high impedance state. (2) At the falling edge of CS, the status of pins from D1 to D12 is loaded to shift register !. (3) At the falling edge of CLK, data which is loaded as above (2) is output to pin DO as 12-bit serial data in order. (4) At the rising edge of CLK, 12-bit serial data is written from DI to shift register @. (5) CLK on and after the 13th bit is neglected and writing of serial data is not possible. Also, DO is put in the high impedance state. (6) At the rising edge of CS, the data which is written as mentioned in (4) is output to pins from D1 to D12. (7) Shift register ! loads the data applied externally and the AND-tie data latched by the parallel output latch. (8) When CS rises before CLK reaches the 12th bit, the parallel output latch latches the data which has been written to shift register @ and outputs it to pins from D1 to D12. In this case, shift registers ! and @ continues the shift operation and DO outputs serial data until CLK reaches the 12th bit. (9) Switching of I/O mode of pins from D1 to D12 is controlled by the serial data which is input to pin DI. Pins to which "H" is written operates as input pins.
OPERATION TIMING DIAGRAM
H S (1) L (2) (5) CLK 1 2 (4) DI DO1 (3) DO DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 High impedance DI10 DI11 DI12 (6) D1 DI1 DO1 3 4 5 6 7 8 9 10 11 12 13 (6)
CS
D2
DI2
DO2
DI2
DI12 1 cycle
DO12
2
MITSUBISHI DIGITAL ASSP
M66006P/FP
12-BIT I/O EXPANDER
ABSOLUTE MAXIMUM RATINGS (Ta = -20 ~ 75C unless otherwise noted)
Symbol VCC VI VO IIK IOK IGND Tstg Supply voltage Input voltage Output voltage Input protection diode current Output parasitic diode current GND current Storage temperature VI<0V VI>VCC VO<0V VO>VCC GND Parameter Conditions Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 -20 20 -20 20 -48 -60 ~ 150 Unit V V V mA mA mA C
RECOMMENDED OPERATIONAL CONDITIONS
Symbol VCC VI VO Topr Parameter Supply voltage Input voltage Output voltage Operating temperature Min. 2 0 0 -20 Limits Typ. Max. 6 VCC VCC 75 Unit V V V C
ELECTRICAL CHARACTERISTICS (VCC = 2 ~ 6V unless otherwise noted)
Symbol Parameter Positive direction threshold voltage *1 Negative direction threshold voltage *1 "H" input voltage *2 "L" input voltage *2 "L" output voltage Maximum output leak current Static power dissipation Test conditions VO=0.1V, VCC-0.1V |IO|=20A VO=0.1V, VCC-0.1V |IO|=20A VO=0.1V, VCC-0.1V |IO|=20A VO=0.1V, VCC-0.1V |IO|=20A VI=VT+, VT- VCC=4.5V VI=VT+, VT- VCC=6V VI=VCC, GND, VCC=6V Limits Ta=25C Min. Typ. Max. 0.35 0.8 x VCC x VCC 0.2 0.65 x VCC x VCC 0.75 x VCC 0.25 x VCC 0.4 1.0 -1.0 10.0 Ta= -20~75C Min. Max. 0.35 0.8 x VCC x VCC 0.2 0.65 x VCC x VCC 0.75 x VCC 0.25 x VCC 0.5 10.0 -10.0 100.0 Unit
VT+ VT- VIH VIL VOL IO ICC
*1: DI, CLK, CS, S *2: D1~D12
V V V V V A A
IOL=3mA VO=VCC VO=GND
SWITCHING CHARACTERISTICS (VCC = 5V)
Limits Symbol fmax tPLZ tPZL tPLZ tPZL tPLZ Parameter Maximum repeat frequency Output "L-Z", "Z-L" propagation time CLK-DO Output "L-Z", "Z-L" propagation time CS-D1 to D12 Output "L-Z" propagation time S-DO, D1 to D12 Test conditions Ta=25C Min. Typ. Max. 2.5 300 300 300 300 300 Ta= -20~75C Min. Max. 1.9 400 400 400 400 400 Unit MHz ns ns ns ns ns
CL=50pF RL=1k (Note 2)
3
MITSUBISHI DIGITAL ASSP
M66006P/FP
12-BIT I/O EXPANDER
TIMING CONDITIONS (VCC = 5V)
Limits Symbol tw tsu Parameter CLK, CS, S pulse width Setup time of DI to CLK Setup time of CS to CLK Setup time of D1 to D12 to CS Hold time of DI to CLK Hold time of CS to CLK Hold time of D1 to D12 to CS Recovery time of CS to S Test conditions Ta=25C Min. Typ. Max. 200 100 100 100 100 100 100 100 Ta= -20~75C Min. Max. 260 130 130 130 130 130 130 130 Unit ns ns
th trec
ns ns
NOTE 2: TEST CIRCUIT
Input
VCC
Output
VCC (1)Characteristics of pulse generator (PG) (10% to 90%) tr=6ns, tf=6ns, Zo=50 RL (2)Static capacitance CL includes floating capacitance of
PG 50
Tested device wiring and input capacitance of probe. CL GND
4
MITSUBISHI DIGITAL ASSP
M66006P/FP
12-BIT I/O EXPANDER
TIMING CHARTS
tw CLK 50% tPLZ DO 50% tw VCC 50% tPZL VCC 10% 50% VOL CS GND 50% GND trec VCC S GND VCC
tw CS 50% tPLZ D1 ~ D12 50%
tw VCC 50% tPZL VCC 50% VOL 50% GND
10%
tw VCC S 50% tPLZ DO D1 ~ D12 VCC 10% VOL 50% GND
VCC DI 50% tsu CLK th VCC 50% GND 50% GND
VCC D1 ~ D12 50% tsu CS th VCC 50% GND 50% GND
VCC CS 50% tsu CLK 50% th VCC 50% GND 50% GND
5

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